This is nice article to start with, but there is one basic limitation that this circuit is preventing +glitches,i.e. there is no problem for +edge trigerred flops on this output clock. Limitation is seen when in design there are both +edge & -ve trigerred flops.
I hope i m clear about my concern....
Regards Navneet mail id: er.navneetgupta@gmail.com
1 comment:
This is nice article to start with, but there is one basic limitation that this circuit is preventing +glitches,i.e. there is no problem for +edge trigerred flops on this output clock. Limitation is seen when in design there are both +edge & -ve trigerred flops.
I hope i m clear about my concern....
Regards
Navneet
mail id: er.navneetgupta@gmail.com
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